In Section 12.7, there's a typo in the discussion of inner/outer loop design

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Edition Second
Version number 3.0h
Submission date 11/22/2016
Your name Chanud Yasanayake
E-mail address cyasanay@caltech.edu
Chapter 12.7
Page number 12-35
Line number 4
Current status Pending

It says "...a "inner/outer" loop design methodology...". It should be "an" instead of "a".